S912XHY128F0VLM Datasheet, PDF (147/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12XHYPIMV1)
Table 2-75. DDRV Register Field Descriptions (continued)
Field
3
DDRV
Description
Port V data direction—
If enabled the Motor driver PWM output it will force the I/O state to be output
Else if IIC is routing to PV and IIC is enabled, it will force the I/O state to be output, also the input buffer is enabled
Else if PWM7 is routing to PV and PWM 7 is configured as PWM channel output, it will force the I/O state to be output
Else if PWM7 is routing to PV and PWM7 is configured as PWM emergency shutdown, it will force the I/O state to
be input
Else if SPI is routing to PV and SPI is enabled, SPI will determine the I/O state.
2
DDRV
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port V data direction—
If enabled the Motor driver PWM output it will force the I/O state to be output
Else if corresponding TIM1 output compare channle is enabled, it will be force as output
Else if SPI is routing to PV and SPI is enabled, SPI will determined the I/O state
Else if PWM6 is routing to PV, it will force the I/O state to be output.
1
DDRV
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port V data direction—
If enabled the Motor driver PWM output it will force the I/O state to be output
Else if SPI is routing to PV and SPI is enabled, SPI will determined the I/O state
Else if PWM5 is routing to PV, it will force I/O state to be output
Else if SPI is routing to PV and SPI is enabled, SPI will determined the I/O state.
0
DDRV
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port V data direction—
If enabled the Motor driver PWM output it will force the I/O state to be output
Else if corresponding TIM1 output compare channel is enabled, it will be forced as output
Else if IIC is routing to PV and IIC is enabled, it will force the I/O state to be output, also the input buffer is enabled
Else if PWM4 is routing to PV, it will force I/O state to be output
Else if SPI is routing to PV and SPI is enabled, SPI will determine the I/O state.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTV or PTIV registers, when changing the
DDRV register.
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
147