S912XHY128F0VLM Datasheet, PDF (287/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12XE Clocks and Reset Generator (S12XECRGV2)
S12XECRG performs a quality check on the incoming clock signal. As soon as clock quality check
indicates a valid Oscillator Clock signal the reset sequence starts using the Oscillator clock. If after 50
check windows the clock quality check indicated a non-valid Oscillator Clock the reset sequence starts
using Self-Clock Mode.
Figure 7-22 and Figure 7-23 show the power-up sequence for cases when the RESET pin is tied to V_DD
and when the RESET pin is held low.
RESET
Clock Quality Check
(no Self-Clock Mode)
)(
Internal POR
Internal RESET
)(
128 SYSCLK
)(
64 SYSCLK
Figure 7-22. RESET Pin Tied to V_DD (by a Pull-up Resistor)
RESET
Clock Quality Check
(no Self Clock Mode)
)(
Internal POR
Internal RESET
)(
128 SYSCLK
)(
64 SYSCLK
Figure 7-23. RESET Pin Held Low Externally
7.6 Interrupts
The interrupts/reset vectors requested by the S12XECRG are listed in Table 7-18. Refer to MCU
specification for related vector addresses and priorities.
Table 7-18. S12XECRG Interrupt Vectors
Interrupt Source
CCR
Mask
Local Enable
Real time interrupt
I bit
LOCK interrupt
I bit
SCM interrupt
I bit
CRGINT (RTIE)
CRGINT (LOCKIE)
CRGINT (SCMIE)
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
287