S912XHY128F0VLM Datasheet, PDF (265/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12XE Clocks and Reset Generator (S12XECRGV2)
Module Base + 0x0002
7
6
5
4
3
2
1
0
R
0
0
0
W
POSTDIV[4:0]
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-5. S12XECRG Post Divider Register (POSTDIV)
Read: Anytime
Write: Anytime except if PLLSEL = 1
f _PLL = ₍---₂---_x---_P---^f-_O-^V----_S-^C--_T--^O--_D-----_I--_V-----₎
NOTE
If POSTDIV = $00 then f_PLL is identical to f_VCO (divide by one).
7.3.2.4 S12XECRG Flags Register (CRGFLG)
This register provides S12XECRG status bits and flags.
Module Base + 0x0003
7
R
RTIF
W
6
PORF
5
LVRF
4
LOCKIF
3
LOCK
2
ILAF
1
SCMIF
0
SCM
Reset
0
Note 1
Note 2
Note 3
0
0
0
0
1. PORF is set to 1 when a power on reset occurs. Unaffected by system reset.
2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by system reset.
3. ILAF is set to 1 when an illegal address reset occurs. Unaffected by system reset. Cleared by power on or low voltage reset.
= Unimplemented or Reserved
Figure 7-6. S12XECRG Flags Register (CRGFLG)
Read: Anytime
Write: Refer to each bit for individual write conditions
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
265