S912XHY128F0VLM Datasheet, PDF (225/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12X Debug (S12XDBGV3) Module
— Loop1: same as Normal but inhibits consecutive duplicate source address entries
— Detail: address and data for all cycles except free cycles and opcode fetches are stored
— Pure PC: All program counter addresses are stored.
• 4-stage state sequencer for trace buffer control
— Tracing session trigger linked to Final State of state sequencer
— Begin, End, and Mid alignment of tracing to trigger
6.1.4 Modes of Operation
The S12XDBG module can be used in all MCU functional modes.
During BDM hardware accesses and whilst the BDM module is active, CPU12X monitoring is disabled.
Thus breakpoints, comparators, and CPU12X bus tracing are disabled . When the CPU12X enters active
BDM Mode through a BACKGROUND command, with the S12XDBG module armed, the S12XDBG
remains armed.
The S12XDBG module tracing is disabled if the MCU is secure. However, breakpoints can still be
generated if the MCU is secure.
BDM
Enable
x
0
0
1
1
BDM
Active
x
0
1
0
1
Table 6-3. Mode Dependent Restriction Summary
MCU
Secure
1
0
0
0
0
Comparator
Matches Enabled
Yes
Yes
Yes
No
Breakpoints
Possible
Tagging
Possible
Yes
Yes
Only SWI
Yes
Active BDM not possible when not enabled
Yes
Yes
No
No
Tracing
Possible
No
Yes
Yes
No
MC9S12XHY-Family Reference Manual Rev. 1.01
Freescale Semiconductor
225