S912XHY128F0VLM Datasheet, PDF (311/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Voltage Regulator (S12VREGL3V3V1)
corresponding deassertion levels, signal LVR deasserts. The LVR function is available only in Full
Performance Mode.
9.4.6 HTD - High Temperature Detect
Subblock HTD is responsible for generating the high temperature interrupt (HTI). HTD monitors the die
temperature T_DIE and continuously updates the status flag HTDS.
Interrupt flag HTIF is set whenever status flag HTDS changes its value.
The HTD is available in FPM and is inactive in Reduced Power Mode and Shutdown Mode.
The HT Trimming bits HTTR[3:0] can be set so that the temperature offset is zero, if accurate temperature
measurement is desired.
See Table 23-16 for the trimming effect of APITR.
9.4.7 Regulator Control (CTRL)
This part contains the register block of VREG_3V3 and further digital functionality needed to control the
operating modes. CTRL also represents the interface to the digital core logic.
9.4.8 Autonomous Periodical Interrupt (API)
Subblock API can generate periodical interrupts independent of the clock source of the MCU. To enable
the timer, the bit APIFE needs to be set.
The API timer is either clocked by a trimmable internal RC oscillator or the bus clock. Timer operation
will freeze when MCU clock source is selected and bus clock is turned off. See CRG specification for
details. The clock source can be selected with bit APICLK. APICLK can only be written when APIFE is
not set.
The APIR[15:0] bits determine the interrupt period. APIR[15:0] can only be written when APIFE is
cleared. As soon as APIFE is set, the timer starts running for the period selected by APIR[15:0] bits. When
the configured time has elapsed, the flag APIF is set. An interrupt, indicated by flag APIF = 1, is triggered
if interrupt enable bit APIE = 1. The timer is started automatically again after it has set APIF.
The procedure to change APICLK or APIR[15:0] is first to clear APIFE, then write to APICLK or
APIR[15:0], and afterwards set APIFE.
The API Trimming bits APITR[5:0] must be set so the minimum period equals 0.2 ms if stable frequency
is desired.
See Table 9-8 for the trimming effect of APITR.
NOTE
The first period after enabling the counter by APIFE might be reduced by
API start up delay t_sdel. The API internal RC oscillator clock is not available
if VREG_3V3 is in Shutdown Mode.
MC9S12XHY-Family Reference Manual Rev. 1.01
Freescale Semiconductor
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