S912XHY128F0VLM Datasheet, PDF (24/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Device Overview MC9S12XHY-Family
Address
Module
0x0240–0x029F
0x02A0–0x02CF
PIM (port integration module)
TIM1(timer module)
0x02D0–0x02EF
0x02F0–0x02F7
0x02F8–0x02FF
0x0300–0x03FF
0x0400–0x07FF
Reserved
Voltage regulator
Reserved
Reserved
Reserved
Size
(Bytes)
96
48
reference
pages
791
795
32
8
797
8
256
1024
NOTE
Reserved register space shown in Table 1-2 is not allocated to any module.
This register space is reserved for future use. Writing to these locations have
no effect. Read access to these locations returns zero.
Figure 1-2 shows MC9S12XHY family CPU and BDM local address translation to the global memory
map. It indicates also the location of the internal resources in the memory map.
Accessing the reserved area in the range of 0x0C00 to 0x0FFF will return undefined data values.
A CPU access to any unimplemented space causes an illegal address reset.
The range between 0x10_0000 and 0x13_FFFF is mapped to DFLASH (Data Flash). The DFLASH block
sizes are listed in Table 1-3.
MC9S12XHY-Family Reference Manual, Rev. 1.01
24
Freescale Semiconductor