S912XHY128F0VLM Datasheet, PDF (88/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12XHYPIMV1)
Table 2-6. DDRA Register Field Descriptions
Field
7-4,2
DDRA
Description
Port A Data Direction—
This bit determines whether the associated pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disable
3
DDRA
1 Associated pin is configured as output
0 Associated pin is configured as input
Port A Data Direction—
This bit determines whether the associated pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
Else if API_EXTCLK is enabled, it will be forced as output
1
DDRA
1 Associated pin is configured as output
0 Associated pin is configured as input
Port A Data Direction—
This bit determines whether the associated pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
Else if XIRQ is enabled, it will be forced as input
0
DDRA
1 Associated pin is configured as output
0 Associated pin is configured as input
Port A Data Direction—
This bit determines whether the associated pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
Else if /IRQ is enabled, it will be forced as input
1 Associated pin is configured as output
0 Associated pin is configured as input
2.3.6 Port B Data Direction Register (DDRB)
Address 0x0003 (PRR)
R
W
Reset
7
DDRB7
0
1 _{Read: Anytime}
Write: Anytime
6
DDRB6
5
DDRB5
4
DDRB4
3
DDRB3
2
DDRB2
0
0
0
0
0
Figure 2-4. Port B Data Direction Register (DDRB)
Access: User read/write¹
1
0
DDRB1
DDRB0
0
0
MC9S12XHY-Family Reference Manual, Rev. 1.01
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Freescale Semiconductor