S912XHY128F0VLM Datasheet, PDF (709/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Stepper Stall Detector (SSDV1) Block Description
NOTE
A separate read/write for high byte and low byte gives a different result than
accessing the register as a word.
If the RDMCL bit in the MDCCTL register is cleared, reads of the MDCCNT register will return the
present value of the count register. If the RDMCL bit is set, reads of the MDCCNT register will return the
contents of the load register.
With a 0x0000 write to the MDCCNT register, the modulus counter stays at zero and does not set the
MCZIF flag in the SSDFLG register.
If modulus mode is not enabled (MODMC = 0), a write to the MDCCNT register immediately updates the
load register and the counter register with the value written to it. The modulus counter will count down
from this value and will stop at 0x0000.
If modulus mode is enabled (MODMC = 1), a write to the MDCCNT register updates the load register with
the value written to it. The count register will not be updated with the new value until the next counter
underflow. The FLMC bit in the MDCCTL register can be used to immediately update the count register
with the new value if an immediate load is desired.
The modulus down counter clock frequency is the bus frequency divided by 64 or 512.
21.3.2.6 Integration Accumulator Register (ITGACC)
Module Base + 0x0006
15
14
13
12
11
10
9
8
R
ITGACC
W
Reset
0
0
0
0
0
0
0
0
Figure 21-8. Integration Accumulator Register High (ITGACC)
Module Base + 0x0007
7
6
5
4
3
2
1
0
R
ITGACC
W
Reset
0
0
0
0
0
0
0
0
Read: anytime.
Figure 21-9. Integration Accumulator Register Low (ITGACC)
Write: Never.
NOTE
A separate read for high byte and low byte gives a different result than
accessing the register as a word.
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
709