S912XHY128F0VLM Datasheet, PDF (107/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12XHYPIMV1)
Table 2-24. Port M Data Register (PTM)
Table 2-25. PTM Register Field Descriptions (continued)
Field
1
PTM
Description
Port M general purpose input/output data—Data Register, SCI1 TXD, PWM channel5,TIM0 output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
0
PTM
• The SCI1 takes precedence over the TIM0 output,PWM5 and general purpose I/O function if enabled
• The TIM0 output function takes precedence over the PWM5 and general purpose I/O function if the related
channel is enabled.³
• The PWM5 takes precedence over the general purpose I/O function if enabled
Port M general purpose input/output data—Data Register, SCI1 RXD, PWM channel4,TIM0 output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The SCI1 takes precedence over the TIM0 output,PWM4 and general purpose I/O function if enabled
• The TIM0 output function takes precedence over the PWM4 and general purpose I/O function if the related
channel is enabled.⁴
• The PWM4 takes precedence over the general purpose I/O function if enabled
1 _{In order TIM input capture to be function correctly, the corresponding DDRT bit should be set to 0}
2 _{In order TIM input capture to be function correctly, the corresponding DDRT bit should be set to 0}
3 _{In order TIM input capture to be function correctly, the corresponding DDRT bit should be set to 0}
4 _{In order TIM input capture to be function correctly, the corresponding DDRT bit should be set to 0}
2.3.32 Port M Input Register (PTIM)
Address 0x0251
7
6
5
4
3
2
R
0
0
0
0
PTIM3
PTIM2
W
Reset
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-29. Port M Input Register (PTIM)
1 _{Read: Anytime}
Write:Never, writes to this register have no effect.
Access: User read¹
1
PTIM1
0
PTIM0
u
u
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
107