S912XHY128F0VLM Datasheet, PDF (342/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Freescale’s Scalable Controller Area Network (S12MSCANV3)
11.1.1 Glossary
ACK
CAN
CRC
EOF
FIFO
IFS
SOF
CPU bus
CAN bus
oscillator clock
bus clock
CAN clock
Table 11-2. Terminology
Acknowledge of CAN message
Controller Area Network
Cyclic Redundancy Code
End of Frame
First-In-First-Out Memory
Inter-Frame Sequence
Start of Frame
CPU related read/write data bus
CAN protocol related serial bus
Direct clock from external oscillator
CPU bus related clock
CAN protocol related clock
11.1.2 Block Diagram
Oscillator Clock
Bus Clock
MSCAN
CANCLK
Tq Clk
MUX
Presc.
Receive/
Transmit
Engine
Transmit Interrupt Req.
Receive Interrupt Req.
Errors Interrupt Req.
Wake-Up Interrupt Req.
Control
and
Status
Configuration
Registers
Message
Filtering
and
Buffering
Wake-Up
Low Pass Filter
Figure 11-1. MSCAN Block Diagram
RXCAN
TXCAN
MC9S12XHY-Family Reference Manual, Rev. 1.01
342
Freescale Semiconductor