S912XHY128F0VLM Datasheet, PDF (765/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Appendix C
PCB Layout Guidelines
PCB Layout Guidelines
C.1 General
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
• Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins .
• Central point of the ground star should be the VSS3 pin.
• Use low ohmic low inductance connections between VSS1, VSS2 and VSS3.
• VSSPLL must be directly connected to VSS3.
• Keep traces of VSSPLL, EXTAL, and XTAL as short as possible and occupied board area for
C12,C11, and Q1 as small as possible.
• Do not place other signals or supplies underneath area occupied by C12,C11, and Q1 and the
connection area to the MCU.
• Central power input should be fed in at the VDDA/VSSA pins.
Example layouts are illustrated on the following pages.
Table C-1. Recommended Decoupling Capacitor Choice
Component
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
Q1
Purpose
V_DDX1 filter capacitor
V_DDM1 filter capacitor
V_DDM2 filter capacitor
V_DDPLL filter capacitor
V_LCD filter capacitor
V_DDX2 filter capacitor
V_DDA filter capacitor
V_DDR filter capacitor
V_DD filter capacitor
V_DDF filter capacitor
OSC load capacitor
OSC load capacitor
Quartz
Type
Value
X7R/tantalum
X7R/tantalum
>=100 nF
>=47 uF
X7R/tantalum
Ceramic X7R
Ceramic X7R
>=47 uF
220 nF
>=100 nF
X7R/tantalum
Ceramic X7R
X7R/tantalum
>=100 nF
>=100 nF
>=100 nF
Ceramic X7R
220 nF
Ceramic X7R
220 nF
From crystal manufacturer
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MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
765