S912XHY128F0VLM Datasheet, PDF (104/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12XHYPIMV1)
2.3.28 Port S Wired-Or Mode Register (WOMS)
Address 0x024E
R
W
Reset
7
WOMS7
0
1 _{Read: Anytime.}
Write: Anytime.
6
WOMS6
5
WOMS5
4
WOMS4
3
WOMS3
2
WOMS2
0
0
0
0
0
Figure 2-26. Port S Wired-Or Mode Register (WOMS)
Access: User read/write¹
1
0
WOMS1
WOMS0
0
0
Table 2-22. WOMS Register Field Descriptions
Field
Description
7-0
WOMS
Port S wired-or mode—Enable wired-or functionality
This register configures the output pins as wired-or. If enabled the output is driven active low only (open-drain). A
logic level of “1” is not driven.This allows a multipoint connection of several serial modules. These bits have no
influence on pins used as inputs.
1 Output buffers operate as open-drain outputs.
0 Output buffers operate as push-pull outputs.
2.3.29 Port S Routing Register (PTSRR)
Address 0x024F
7
R
0
W
Reset
0
1 _{Read: Anytime.}
Write: Anytime.
6
5
4
3
2
0
0
0
PTSRR5
PTSRR4
0
0
0
0
0
Figure 2-27. Port S Routing Register (PTSRR)
This register configures the re-routing of IIC and SPI on alternative ports.
Access: User read/write¹
1
0
PTSRR1 PTSRR0
0
0
Table 2-23. Module Routing Summary
Module
PTSRR
Related Pins
54 10
SCL
SDA
MC9S12XHY-Family Reference Manual, Rev. 1.01
104
Freescale Semiconductor