S912XHY128F0VLM Datasheet, PDF (223/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Chapter 6
S12X Debug (S12XDBGV3) Module
Table 6-1. Revision History
Revision
Number
Revision Date
V03.20 14 Sep 2007
V03.21 23 Oct 2007
V03.22
V03.23
V03.24
V03.25
12 Nov 2007
13 Nov 2007
04 Jan 2008
14 May 2008
Sections
Affected
Description of Changes
6.3.2.7/6-233 - Clarified reserved State Sequencer encodings.
6.4.2.2/6-246 - Added single databyte comparison limitation information
6.4.2.4/6-247 - Added statement about interrupt vector fetches whilst tagging.
6.4.5.2/6-251 - Removed LOOP1 tracing restriction NOTE.
6.4.5.5/6-255 - Added pin reset effect NOTE.
General - Text readability improved, typo removed.
6.4.5.3/6-253 - Corrected bit name.
- Updated Revision History Table format. Corrected other paragraph formats.
6.1 Introduction
The S12XDBG module provides an on-chip trace buffer with flexible triggering capability to allow non-
intrusive debug of application software. The S12XDBG module is optimized for the S12X 16-bit
architecture and allows debugging of CPU12X module operations.
Typically the S12XDBG module is used in conjunction with the S12XBDM module, whereby the user
configures the S12XDBG module for a debugging session over the BDM interface. Once configured the
S12XDBG module is armed and the device leaves BDM Mode returning control to the user program,
which is then monitored by the S12XDBG module. Alternatively the S12XDBG module can be configured
over a serial interface using SWI routines.
6.1.1 Glossary
Table 6-2. Glossary Of Terms
Term
COF
BDM
DUG
WORD
Data Line
Definition
Change Of Flow.
Change in the program flow due to a conditional branch, indexed jump or interrupt
Background Debug Mode
Device User Guide, describing the features of the device into which the DBG is integrated
16 bit data entity
64 bit data entity
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
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