S912XHY128F0VLM Datasheet, PDF (51/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Device Overview MC9S12XHY-Family
1.8 System Clock Description
For the LCD CLK in Table 1-8. LCD Clock and Frame Frequency, it is always connected to the CRG LCD
clok output, which is from OSC clock, see Figure 7-16. System Clocks Generator.The clock and reset
generator module (CRG) provides the internal clock signals for the core and all peripheral modules.
Figure 1-5 shows the clock connections from the CRG to all modules.
Consult the S12XECRG section for details on clock generation.
NOTE
The XHY and XS family uses the XE family clock and reset generator
module. Therefore all CRG references are related to S12XECRG.
SCI0 . . SCI 1
CAN0..CAN1
IIC
SPI0
ATD0
LCD
Bus Clock
EXTAL
XTAL
CRG
Oscillator Clock
Lcd Clock
Core Clock
SSD
MC
TIM
PIM
RAM
S12X
FLASH
PWM
Figure 1-5. Clock Connections
The system clock can be supplied in several ways enabling a range of system operating frequencies to be
supported:
• The on-chip phase locked loop (PLL)
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
51