S912XHY128F0VLM Datasheet, PDF(301/802 Page) Freescale Semiconductor, Inc – S12 Microcontrollers

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S912XHY128F0VLM Datasheet, PDF (301/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

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Voltage Regulator (S12VREGL3V3V1)

In Shutdown Mode an external supply driving VDD/VSS can replace the voltage regulator.

9.2.4 VDDF â Regulator Output2 (NVM Logic) Pins

Signals VDDF/VSS are the secondary outputs of VREG_3V3 that provide the power supply for the NVM

logic. These signals are connected to device pins to allow external decoupling capacitors (220 nF, X7R

ceramic).

In Shutdown Mode an external supply driving VDDF/VSS can replace the voltage regulator.

9.2.5 VDDPLL, VSSPLL â Regulator Output3 (PLL) Pins

Signals VDDPLL/VSSPLL are the secondary outputs of VREG_3V3 that provide the power supply for

the PLL and oscillator. These signals are connected to device pins to allow external decoupling capacitors

(100 nF...220 nF, X7R ceramic).

In Shutdown Mode, an external supply driving VDDPLL/VSSPLL can replace the voltage regulator.

9.2.6 VDDX â Power Input Pin

Signals VDDX/VSS are monitored by VREG_3V3 with the LVR feature.

9.2.7 VREGEN â Optional Regulator Enable Pin

This optional signal is used to shutdown VREG_3V3. In that case, VDD/VSS and VDDPLL/VSSPLL

must be provided externally. Shutdown mode is entered with VREGEN being low. If VREGEN is high,

the VREG_3V3 is either in Full Performance Mode or in Reduced Power Mode.

For the connectivity of VREGEN, see device speciï¬cation.

NOTE

Switching from FPM or RPM to shutdown of VREG_3V3 and vice versa

is not supported while MCU is powered.

9.2.8 VREG_API â Optional Autonomous Periodical Interrupt Output Pin

This pin provides the signal selected via APIEA if system is set accordingly. See 9.3.2.3, âAutonomous

Periodical Interrupt Control Register (VREGAPICL) and 9.4.8, âAutonomous Periodical Interrupt (API)

for details.

For the connectivity of VREG_API, see device speciï¬cation.

9.3 Memory Map and Register Deï¬nition

This section provides a detailed description of all registers accessible in VREG_3V3.

If enabled in the system, the VREG_3V3 will abort all read and write accesses to reserved registers within

itâs memory slice. See device level speciï¬cation for details.

MC9S12XHY-Family Reference Manual Rev. 1.01

Freescale Semiconductor

301

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