S912XHY128F0VLM Datasheet, PDF (779/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Detailed Register Address Map
(continued)0x00C8–0x00CF Asynchronous Serial Interface (SCI0) Map
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
R
0
0x00CD SCI0SR2
AMAP
W
0
TXPOL RXPOL
R R8
0
0
0
0x00CE SCI0DRH
T8
W
R R7
R6
R5
R4
R3
0x00CF SCI0DRL
W T7
T6
T5
T4
T3
1 ^{Those registers are accessible if the AMAP bit in the SCI0SR2 register is set to zero}
2 ^{Those registers are accessible if the AMAP bit in the SCI0SR2 register is set to one}
Bit 2
BRK13
0
R2
T2
Bit 1
TXDIR
0
R1
T1
Bit 0
RAF
0
R0
T0
0x00D0–0x00D7 Asynchronous Serial Interface (SCI1) Map
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0x00D0
0x00D1
SCI1BDH^{1 R} IREN
W
SCI1BDL^{1 R} SBR7
W
TNP1
SBR6
TNP0
SBR5
SBR12 SBR11
SBR4
SBR3
0x00D2
SCI1CR1¹
R
LOOPS
SCISWAI
RSRC
M
WAKE
W
0x00D0
SCI1ASR1²
R
RXEDGIF
0
0
0
0
W
0x00D1
SCI1ACR1²
R
RXEDGIE
0
0
0
0
W
0x00D2 SCI1ACR2^{2 R}
0
0
0
0
0
W
R
0x00D3 SCI1CR2
TIE
TCIE
RIE
ILIE
TE
W
R TDRE
TC
RDRF
IDLE
OR
0x00D4 SCI1SR1
W
R
0
0x00D5 SCI1SR2
AMAP
W
0
TXPOL RXPOL
R R8
0
0
0
0x00D6 SCI1DRH
T8
W
R R7
R6
R5
R4
R3
0x00D7 SCI1DRL
W T7
T6
T5
T4
T3
1 ^{Those registers are accessible if the AMAP bit in the SCI1SR2 register is set to zero}
2 ^{Those registers are accessible if the AMAP bit in the SCI1SR2 register is set to one}
Bit 2
SBR10
Bit 1
SBR9
SBR2
SBR1
ILT
PE
BERRV
0
BERRIF
BERRIE
BERRM1 BERRM0
RE
RWU
NF
FE
BRK13
0
TXDIR
0
R2
R1
T2
T1
Bit 0
SBR8
SBR0
PT
BKDIF
BKDIE
BKDFE
SBK
PF
RAF
0
R0
T0
0x00D8–0x00DF Serial Peripheral Interface (SPI) Map
Address
0x00D8
0x00D9
Name
SPICR1
SPICR2
Bit 7
R
SPIE
W
R
0
W
Bit 6
SPE
XFRW
Bit 5
Bit 4
Bit 3
SPTIE
0
MSTR
CPOL
MODFEN BIDIROE
Bit 2
CPHA
0
Bit 1
SSOE
SPISWAI
Bit 0
LSBFE
SPC0
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
779