S912XHY128F0VLM Datasheet, PDF (184/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Interrupt (S12XINTV2)
4.1.4 Block Diagram
Figure 4-1 shows a block diagram of the XINT module.
Peripheral
Interrupt Requests
Non I Bit Maskable
Channels
IRQ Channel
Wake Up
CPU
Vector
Address
RQST
One Set Per Channel
(Up to 108 Channels)
XGATE
Requests
PRIOLVL2
PRIOLVL1
PRIOLVL0
Interrupt
Requests
INT_XGPRIO
IVBR
New
IPL
Current
IPL
Priority
Decoder
Wake up
XGATE
Vector
ID
XGATE
Interrupts
To XGATE Module
RQST
XGATE Request Route,
PRIOLVLn Priority Level
= bits from the channel configuration
in the associated configuration register
INT_XGPRIO = XGATE Interrupt Priority
IVBR
= Interrupt Vector Base
IPL
= Interrupt Processing Level
Figure 4-1. XINT Block Diagram
4.2 External Signal Description
The XINT module has no external signals.
MC9S12XHY-Family Reference Manual, Rev. 1.01
184
Freescale Semiconductor