S912XHY128F0VLM Datasheet, PDF (578/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

256 KByte Flash Module (S12XFTMR256K1V1)
Table 18-4. FCLKDIV Field Descriptions
Field
Description
7
FDIVLD
6–0
FDIV[6:0]
Clock Divider Loaded
0 FCLKDIV register has not been written
1 FCLKDIV register has been written since the last reset
Clock Divider Bits — FDIV[6:0] must be set to effectively divide OSCCLK down to generate an internal Flash
clock, FCLK, with a target frequency of 1 MHz for use by the Flash module to control timed events during program
and erase algorithms. Table 18-5 shows recommended values for FDIV[6:0] based on OSCCLK frequency.
Please refer to Section 18.4.1, “Flash Command Operations,” for more information.
CAUTION
The FCLKDIV register should never be written while a Flash command is
executing (CCIF=0). The FCLKDIV register is writable during the Flash
reset sequence even though CCIF is clear.
MC9S12XHY-Family Reference Manual, Rev. 1.01
578
Freescale Semiconductor