S912XHY128F0VLM Datasheet, PDF (283/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12XE Clocks and Reset Generator (S12XECRGV2)
7.4.3.3 Stop Mode
All clocks are stopped in STOP mode, dependent of the setting of the PCE, PRE, LCD enable (see
documentation of LCD module) and PSTP bit. The oscillator is disabled in STOP mode unless the PSTP
bit is set. If the PRE or PCE bits are set, the RTI or COP continues to run in Pseudo Stop Mode. In addition
to disabling system and core clocks the S12XECRG requests other functional units of the MCU (e.g.
voltage-regulator) to enter their individual power saving modes (if available).
If the PLLSEL bit is still set when entering Stop Mode, the S12XECRG will switch the system and core
clocks to OSCCLK by clearing the PLLSEL bit. Then the S12XECRG disables the IPLL, disables the core
clock and finally disables the remaining system clocks.
If Pseudo Stop Mode is entered from Self-Clock Mode the S12XECRG will continue to check the clock
quality until clock check is successful. In this case the IPLL and the voltage regulator (VREG) will remain
enabled. If Full Stop Mode (PSTP = 0) is entered from Self-Clock Mode the ongoing clock quality check
will be stopped. A complete timeout window check will be started when Stop Mode is left again.
There are two ways to restart the MCU from Stop Mode:
1. Any reset
2. Any interrupt
If the MCU is woken-up from Full Stop Mode by an interrupt and the fast wake-up feature is enabled
(FSTWKP=1 and SCME=1), the system will immediately (no clock quality check) resume operation in
Self-Clock Mode (see Section 7.4.1.4, “Clock Quality Checker”). The SCMIF flag will not be set for this
special case. The system will remain in Self-Clock Mode with oscillator disabled until FSTWKP bit is
cleared. The clearing of FSTWKP will start the oscillator and the clock quality check. If the clock quality
check is successful, the S12XECRG will switch all system clocks to oscillator clock. The SCMIF flag will
be set. See application examples in Figure 7-19 and Figure 7-20.
Because the IPLL has been powered-down during Stop Mode the PLLSEL bit is cleared and the MCU runs
on OSCCLK after leaving Stop-Mode. The software must manually set the PLLSEL bit again, in order to
switch system and core clocks to the PLLCLK.
NOTE
In Full Stop Mode or Self-Clock Mode caused by the fast wake-up feature
the clock monitor and the oscillator are disabled.
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
283