S912XHY128F0VLM Datasheet, PDF (66/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12XHYPIMV1)
Version
Number
0.10
0.11
Revision
Date
03 Jun
2010
15 Nov
2010
Effective
Date
2.1 Introduction
Author
Description of Changes
fix on page 2-146, no open drain output when portV route to IIC
fix Table 2-1., “Pin Functions and Priorities, PM[1:0] connect to SCI
add NCLKX2 bit on ECLKCTL register2.3.10/2-91
fix typo,it is PTIM and PTM 2.3.16/2-95
remove Reduced drive at section 2.4.2.4 and 2.3.2/2-84
fix table Table 2-1./2-67, PM[1:0] is for TXD/RXD
fix table Table 2-16./2-97, PTTRR[4], PT4 instead of PT6
2.1.1 Overview
The S12XHY Family Port Integration Module establishes the interface between the peripheral modules
and the I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and
multiplexing on shared pins.
This document covers:
• Port A associated with the XLKS,IRQ, XIRQ interrupt inputs and API_EXTCLK. Also associated
with the LCD driver output
• Port B used as general purpose I/O and LCD driver output(including BP and FP pins)
• Port R associated with 2 timer module - port 4:0 inputs can be used as an external interrupt
source.Also associated with the LCD driver output. PR also associated with the IIC and CAN1
• Port T associated with 2 timer module. Also associated with the LCD driver output. It can be used
as external interrupt source
• Port S associated with 1 SPI module, 1 SCI module, 1 IIC module and 1 MSCAN, and PWM. Port
6-5and 3-2 can be used as an external interrupt source.
• Port P connected to the PWM, also associated with LCD driver output
• Port H associated with 1 SPI, 1 SCI. Also associated with LCD driver output
• Port M associated with SCI1 PWM and TIM
• Port AD associated with one 12-channel ATD module. It an be used as an external interrupt source
• Port U/V associated with the Motor driver output. Also PV3-0 associated with 1 SPI, 1 IIC and 4
PWM channels. PU0/PU2/PU4/PU6 and PV0/PV2/PV4/PV6 associated with TIM0 channels 0 -3
and TIM1 channels 0 -3
Most I/O pins can be configured by register bits to select data direction, to enable and select pull-up or
pull-down devices. Port U/V have register bits to select the slew rate control.
NOTE
This document assumes the availability of all features (112-pin package
option). Some functions are not available on lower pin count package
options. Refer to the pin-out summary section.
MC9S12XHY-Family Reference Manual, Rev. 1.01
66
Freescale Semiconductor