S912XHY128F0VLM Datasheet, PDF (302/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Voltage Regulator (S12VREGL3V3V1)
9.3.1 Module Memory Map
A summary of the registers associated with the VREG_3V3 sub-block is shown in Table 9-3. Detailed
descriptions of the registers and bits are given in the subsections that follow
Address Name
R
0x02F0 VREGHTCL
W
Bit 7
0
6
5
4
3
2
1
Bit 0
0
HTDS
VSEL
VAE
HTEN
HTIE
HTIF
R
0
0
0
0
0
LVDS
0x02F1 VREGCTRL
LVIE
LVIF
W
0x02F2
VREGAPIC R
L
W
APICLK
0x02F3
VREGAPIT R
R
W
APITR5
0
APITR4
0
APITR3
APIFES
APITR2
APIEA
APITR1
APIFE
APITR0
APIE
0
APIF
0
0x02F4
VREGAPIR R
H
W
APIR15
APIR14
APIR13
APIR12
APIR11
APIR10
APIR9
APIR8
0x02F5
VREGAPIR R
L
W
APIR7
APIR6
APIR5
APIR4
APIR3
APIR2
APIR1
APIR0
0x02F6
Reserved R
06
W
0
0
0
0
0
0
0
0
R
0x02F7 VREGHTTR
HTOEN
W
0
0
0
HTTR3
Table 9-3. Register Summary
HTTR2
HTTR1
HTTR0
MC9S12XHY-Family Reference Manual, Rev. 1.01
302
Freescale Semiconductor