S912XHY128F0VLM Datasheet, PDF (58/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Device Overview MC9S12XHY-Family
Table 1-11. Interrupt Vector Locations (Sheet 3 of 3)
Vector Address⁽¹⁾
Interrupt Source
CCR
Mask
Vector base + $7C
High Temperature Interrupt(HTI)
I bit
Vector base + $7A
CAN1 wake-up
I bit
Vector base + $78
CAN1 errors
I bit
Vector base + $76
CAN1 receive
I bit
Vector base + $74
CAN1 transmit
I bit
Vector base + $72
to
Vector base + $40
Reserved
Vector base + $3E
ATD Compare Interrupt
I bit
Vector base + $3C
to
Vector base + $14
Reserved
Vector base + $12
System Call Interrupt (SYS)
—
Vector base + $10
Spurious interrupt
—
1. 16 bits vector address based
Local Enable
VREGHTCL (HTIE)
CANRIER (WUPIE)
CANRIER (CSCIE, OVRIE)
CANRIER (RXFIE)
CANTIER (TXEIE[2:0])
ATDCTL2 (ACMPIE)
None
None
NOTE
9S12HY64 family LVI/API/HTI vector number is $8A-$86,
while 9S12XHY256 is $80-$7C;9S12HY64 family ATD
Compare interrupt number is $84, while 9S12HY64 family is
$3E;9S12HY64 family has no SYS vector; 9S12HY64 family
Spurious interrupt vector number is $80.
1.11.3 Effects of Reset
When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block sections
for register reset states.
On each reset, the Flash module executes a reset sequence to load Flash configuration registers.
1.11.3.1 Flash Configuration Reset Sequence Phase
On each reset, the Flash module will hold CPU activity while loading Flash module registers from the
Flash memory. If double faults are detected in the reset phase, Flash module protection and security may
be active on leaving reset. This is explained in more detail in the Flash module section.
MC9S12XHY-Family Reference Manual, Rev. 1.01
58
Freescale Semiconductor