S912XHY128F0VLM Datasheet, PDF (707/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Stepper Stall Detector (SSDV1) Block Description
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Table 21-8. SSDCTL Field Descriptions
Field
Description
7
RTZE
6
SDCPU
5
SSDWAI
4
FTST
1:0
ACLKS
Return to Zero Enable — If this bit is set, the coils are controlled by the SSD and are configured into one of the
four full step states as shown in Table 21-6. If this bit is cleared, the coils are not controlled by the SSD.
0 RTZ is disabled.
1 RTZ is enabled.
Sigma-Delta Converter Power Up — This bit provides on/off control for the sigma-delta converter allowing
reduced MCU power consumption. Because the analog circuit is turned off when powered down, the sigma-delta
converter requires a recovery time after it is powered up.
0 Sigma-delta converter is powered down.
1 Sigma-delta converter is powered up.
SSD Disabled during Wait Mode — When entering Wait Mode, this bit provides on/off control over the SSD
allowing reduced MCU power consumption. Because the analog circuit is turned off when powered down, the
sigma-delta converter requires a recovery time after exit from Wait Mode.
0 SSD continues to run in WAIT mode.
1 Entering WAIT mode freezes the clock to the prescaler divider, powers down the sigma-delta converter, and
if RTZE bit is set, the sine and cosine coils are recirculated via VSSM.
Factory Test — This bit is reserved for factory test and reads zero in user mode.
Accumulator Sample Frequency Select — This field sets the accumulator sample frequency by pre-scaling
the bus frequency by a factor of 8, 16, 32, or 64. A faster sample frequency can provide more accurate results
but cause the accumulator to overflow. Best results are achieved with a frequency between 500 kHz and 2 MHz.
Accumulator Sample Frequency = f_BUS / (8 x 2^ACLKS)
Table 21-9. Accumulator Sample Frequency
ACLKS
0
1
2
3
Frequency
f_BUS / 8
f_BUS / 16
f_BUS / 32
f_BUS / 64
f_BUS = 40
MHz
5.00 MHz
2.50 MHz
1.25 MHz
625 kHz
f_BUS = 25
MHz
3.12 MHz
1.56 MHz
781 kHz
391 kHz
f_BUS = 16
MHz
2.00 MHz
1.00 MHz
500 kHz
250 kHz
NOTE
A change in the accumulator sample frequency will not be effective until the
ITG bit is cleared.
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
707