S912XHY128F0VLM Datasheet, PDF (163/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Memory Mapping Control (S12XMMCV4)
3.3.2.2 Global Page Index Register (GPAGE)
Address: 0x0010
7
R
0
W
6
GP6
5
GP5
4
GP4
Reset
0
0
0
0
= Unimplemented or Reserved
3
GP3
0
2
GP2
0
1
GP1
0
0
GP0
0
Figure 3-6. Global Page Index Register (GPAGE)
Read: Anytime
Write: Anytime
The global page index register is used to construct a 23 bit address in the global map format. It is only used
when the CPU is executing a global instruction (GLDAA, GLDAB, GLDD, GLDS, GLDX,
GLDY,GSTAA, GSTAB, GSTD, GSTS, GSTX, GSTY) (see CPU Block Guide). The generated global
address is the result of concatenation of the CPU local address [15:0] with the GPAGE register [22:16] (see
Figure 3-7).
Bit22
Global Address [22:0]
Bit16 Bit15
Bit 0
GPAGE Register [6:0]
CPU Address [15:0]
Figure 3-7. GPAGE Address Mapping
Table 3-4. GPAGE Field Descriptions
Field
6–0
GP[6:0]
Description
Global Page Index Bits 6–0 — These page index bits are used to select which of the 128 64KB pages is to be
accessed.
Example 3-1. This example demonstrates usage of the GPAGE register
LDX
MOVB
GLDAA
#0x5000
#0x14, GPAGE
X
;Set GPAGE offset to the value of 0x5000
;Initialize GPAGE register with the value of 0x14
;Load Accu A from the global address 0x14_5000
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
163