S912XHY128F0VLM Datasheet, PDF (146/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12XHYPIMV1)
Field
7-0
PTIV
Table 2-74. PTIV Register Field Descriptions
Description
Port V input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
2.3.91 Port V Data Direction Register (DDRV)
Address 0x029A
R
W
Reset
7
DDRV7
0
1 _{Read: Anytime.}
Write: Anytime.
6
DDRV6
5
DDRV5
4
DDRV4
3
DDRV3
2
DDRV2
0
0
0
0
0
Figure 2-88. Port V Data Direction Register (DDRV)
Access: User read/write¹
1
0
DDRV1
DDRV0
0
0
Table 2-75. DDRV Register Field Descriptions
Field
7
DDRV
Description
Port V data direction—
If enabled the Motor driver PWM output it will force the I/O state to be output.
6
DDRV
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port V data direction—
If enabled the Motor driver PWM output or enable the TIM1 channel 3 output compare function, it will force the I/O
state to be output.
5
DDRV
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port V data direction—
If enabled the Motor driver PWM output it will force the I/O state to be output.
4
DDRV
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port V data direction—
If enabled the Motor driver PWM output or enable the TIM1 channel 2 output compare function, it will force the I/O
state to be output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
MC9S12XHY-Family Reference Manual, Rev. 1.01
146
Freescale Semiconductor