S912XHY128F0VLM Datasheet, PDF (121/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12XHYPIMV1)
1 _{Read: Anytime.}
Write: Anytime.
Table 2-43. PPSH Register Field Descriptions
Field
7-0
PPSH
Description
Port H pull device select—Determine pull device polarity on input pins
This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up
or pull-down device if enabled.
1 A rising edge on the associated Port H pin sets the associated flag bit in the PIFH register. A pull-down device is
connected to the associated Port H pin, if enabled by the associated bit in register PERH and if the port is used
as input.
0 A falling edge on the associated Port H pin sets the associated flag bit in the PIFH register.A pull-up device is
connected to the associated Port H pin, if enabled by the associated bit in register PERH and if the port is used
as input.
2.3.53 Port H Wired-Or Mode Register (WOMH)
Address 0x0266
R
W
Reset
7
WOMH7
0
1 _{Read: Anytime.}
Write: Anytime.
6
WOMH6
5
WOMH5
4
WOMH4
3
WOMH3
2
WOMH2
0
0
0
0
0
Figure 2-50. Port H Wired-Or Mode Register (WOMH)
Access: User read/write¹
1
0
WOMH1
WOMH0
0
0
Table 2-44. WOMS Register Field Descriptions
Field
Description
7-0
WOMH
Port H wired-or mode—Enable wired-or functionality
This register configures the output pins as wired-or. If enabled the output is driven active low only (open-drain). A
logic level of “1” is not driven.This allows a multipoint connection of several serial modules. These bits have no
influence on pins used as inputs.
1 Output buffers operate as open-drain outputs.
0 Output buffers operate as push-pull outputs.
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
121