S912XHY128F0VLM Datasheet, PDF (196/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Interrupt (S12XINTV2)
Stacked IPL
0
0
4
0
0
0
IPL in CCR
Processing Levels
0
4
7
4
3
7
6
L7
RTI
5
4
3
2
L4
RTI
L3 (Pending)
1
L1 (Pending)
0
Reset
Figure 4-14. Interrupt Processing Example
1
RTI
0
RTI
4.5.3 Wake Up from Stop or Wait Mode
4.5.3.1 CPU Wake Up from Stop or Wait Mode
Every I bit maskable interrupt request which is configured to be handled by the CPU is capable of waking
the MCU from stop or wait mode. To determine whether an I bit maskable interrupts is qualified to wake
up the CPU or not, the same settings as in normal run mode are applied during stop or wait mode:
• If the I bit in the CCR is set, all I bit maskable interrupts are masked from waking up the MCU.
• An I bit maskable interrupt is ignored if it is configured to a priority level below or equal to the
current IPL in CCR.
• I bit maskable interrupt requests which are configured to be handled by the XGATE module are not
capable of waking up the CPU.
The X bit maskable interrupt request can wake up the MCU from stop or wait mode at anytime, even if the
X bit in CCR is set. If the X bit maskable interrupt request is used to wake-up the MCU with the X bit in
the CCR set, the associated ISR is not called. The CPU then resumes program execution with the
instruction following the WAI or STOP instruction. This features works following the same rules like any
interrupt request, i.e. care must be taken that the X interrupt request used for wake-up remains active at
least until the system begins execution of the instruction following the WAI or STOP instruction;
otherwise, wake-up may not occur.
4.5.3.2 XGATE Wake Up from Stop or Wait Mode
Interrupt request channels which are configured to be handled by the XGATE module are capable of
waking up the XGATE module. Interrupt request channels handled by the XGATE module do not affect
the state of the CPU.
MC9S12XHY-Family Reference Manual, Rev. 1.01
196
Freescale Semiconductor