S912XHY128F0VLM Datasheet, PDF (111/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12XHYPIMV1)
2.3.38 PIM Reserved Register
Address 0x0257
7
R
0
W
Reset
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-35. PIM Reserved Register
Access: User read¹
1
0
0
0
0
0
2.3.39 Port P Data Register (PTP)
Address 0x0258
R
W
Altern.
Function
Reset
7
PTP7
PWM7
FP7
0
1 _{Read: Anytime.}
Write: Anytime.
6
PTP6
5
PTP5
4
PTP4
3
PTP3
2
PTP2
PWM6
FP6
0
PWM5
PWM4
PWM3
PWM2
FP5
FP4
FP3
FP2
0
0
0
0
Figure 2-36. Port P Data Register (PTP)
Access: User read/write¹
1
0
PTP1
PTP0
PWM1
FP1
0
PWM0
FP0
0
Field
7-0
PTP
Table 2-31. PTP Register Field Descriptions
Description
Port P general purpose input/output data—Data Register, LCD segment driver output, PWM channel output
Port P pins are associated with the PWM channel output and LCD segment driver output.
When not used with the alternative functions, these pins can be used as general purpose I/O. If the associated data
direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input
state is read.
• The LCD segment takes precedence over the PWM function and the general purpose I/O function is LCD
segment output is enabled
• The PWM function takes precedence over the general purpose I/O function if the PWM channel is enabled.
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
111