S912XHY128F0VLM Datasheet, PDF (122/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12XHYPIMV1)
2.3.54 Port H Routing Register (PTHRR)
Address 0x0267
7
6
5
4
3
2
R
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
1 _{Read: Always reads 0x00}
Write: Unimplemented
Figure 2-51. Port HRouting Register (PTHRR)
This register configures the re-routing of SCI1 on alternative pins on Port M/H.
Table 2-45. Port H Routing Register Field Descriptions
Field
0
Port H Routing Register—
PTHRR This register controls the routing of SCI1.
0 SCI1 routed to PH[1:0]
1 SCI1 routed to PM[1:0]
Description
2.3.55 PIM Reserved Register
Address 0x0268-0x26F
7
6
5
4
3
2
R
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
1 _{Read: Always reads 0x00}
Write: Unimplemented
Figure 2-52. PIM Reserved Register
Access: User read¹
1
0
0
PTHRR0
0
0
Access: User read¹
1
0
0
0
0
0
MC9S12XHY-Family Reference Manual, Rev. 1.01
122
Freescale Semiconductor