S912XHY128F0VLM Datasheet, PDF (290/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Pierce Oscillator (S12XOSCLCPV2)
8.1.3 Block Diagram
Figure 8-1 shows a block diagram of the XOSC.
Clock
Monitor
Monitor_Failure
OSCCLK
Peak
Detector
Gain Control
V_DDPLL = 1.8 V
EXTAL
Rf
XTAL
Figure 8-1. XOSC Block Diagram
8.2 External Signal Description
This section lists and describes the signals that connect off chip
8.2.1 VDDPLL and VSSPLL — Operating and Ground Voltage Pins
Theses pins provides operating voltage (V_DDPLL) and ground (V_SSPLL) for the XOSC circuitry. This
allows the supply voltage to the XOSC to use an independent bypass capacitor.
8.2.2 EXTAL and XTAL — Input and Output Pins
These pins provide the interface for either a crystal or a 1.8V CMOS compatible clock to control the
internal clock generator circuitry. EXTAL is the external clock input or the input to the crystal oscillator
amplifier. XTAL is the output of the crystal oscillator amplifier. The MCU internal system clock is derived
MC9S12XHY-Family Reference Manual, Rev. 1.01
290
Freescale Semiconductor