S912XHY128F0VLM Datasheet, PDF (645/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

128 KByte Flash Module (S12XFTMR128K1V1)
Offset Module Base + 0x0013
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-22. Flash Reserved4 Register (FRSV4)
All bits in the FRSV4 register read 0 and are not writable.
19.3 Functional Description
19.3.1 Flash Command Operations
Flash command operations are used to modify Flash memory contents.
The next sections describe:
• How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from
OSCCLK for Flash program and erase command operations
• The command write sequence used to set Flash command parameters and launch execution
• Valid Flash commands available for execution
19.3.1.1 Writing the FCLKDIV Register
Prior to issuing any Flash program or erase command after a reset, the user is required to write the
FCLKDIV register to divide OSCCLK down to a target FCLK of 1 MHz. Table 19-4 shows recommended
values for the FDIV field based on OSCCLK frequency.
NOTE
Programming or erasing the Flash memory cannot be performed if the bus
clock runs at less than 1 MHz. Setting FDIV too high can destroy the Flash
memory due to overstress. Setting FDIV too low can result in incomplete
programming or erasure of the Flash memory cells.
When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the
FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written,
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
645