S912XHY128F0VLM Datasheet, PDF (785/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Detailed Register Address Map
Detailed MSCAN Foreground Receive and Transmit Buffer Layout (continued)
Address Name
Extended ID R
CANxTIDR3 W
0xXX13
Standard ID R
W
0xXX14- CANxTDSR0– R
0xXX1B CANxTDSR7 W
R
0xXX1C CANxTDLR
W
R
0xXX1D CANxTTBPR
W
R
0xXX1E CANxTTSRH
W
R
0xXX1F CANxTTSRL
W
Bit 7
ID6
DB7
PRIO7
TSR15
TSR7
Bit 6
ID5
DB6
PRIO6
TSR14
TSR6
Bit 5
ID4
DB5
PRIO5
TSR13
TSR5
Bit 4
ID3
DB4
PRIO4
TSR12
TSR4
Bit 3
ID2
DB3
DLC3
PRIO3
TSR11
TSR3
Bit 2
ID1
DB2
DLC2
PRIO2
TSR10
TSR2
Bit 1
ID0
DB1
DLC1
PRIO1
TSR9
TSR1
Bit 0
RTR
DB0
DLC0
PRIO0
TSR8
TSR0
0x0180–0x01BF MSCAN (CAN1) Map
Address Name
Bit 7
0x0180
0x0181
0x0182
0x0183
0x0184
0x0185
0x0186
0x0187
0x0188
0x0189
0x018A
0x018B
0x018C
R
CAN1CTL0
RXFRM
W
R
CAN1CTL1
CANE
W
R
CAN1BTR0
SJW1
W
R
CAN1BTR1
SAMP
W
R
CAN1RFLG
WUPIF
W
R
CAN1RIER
WUPIE
W
R
0
CAN1TFLG
W
R
0
CAN1TIER
W
R
0
CAN1TARQ
W
R
0
CAN1TAAK
W
R
0
CAN1TBSEL
W
R
0
CAN1IDAC
W
R
0
Reserved
W
Bit 6
RXACT
Bit 5
CSWAI
Bit 4
SYNCH
CLKSRC LOOPB LISTEN
Bit 3
TIME
BORM
Bit 2
WUPE
WUPM
Bit 1
SLPRQ
SLPAK
Bit 0
INITRQ
INITAK
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
TSEG22
CSCIF
TSEG21
RSTAT1
TSEG20
RSTAT0
TSEG13
TSTAT1
TSEG12
TSTAT0
TSEG11
OVRIF
TSEG10
RXF
CSCIE
0
0
0
0
RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE
0
0
0
TXE2
TXE1
TXE0
0
0
0
TXEIE2 TXEIE1 TXEIE0
0
0
0
ABTRQ2 ABTRQ1 ABTRQ0
0
0
0
ABTAK2 ABTAK1 ABTAK0
0
0
0
0
TX2
TX1
TX0
0
0
IDHIT2 IDHIT1 IDHIT0
IDAM1 IDAM0
0
0
0
0
0
0
0
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
785