S912XHY128F0VLM Datasheet, PDF (270/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12XE Clocks and Reset Generator (S12XECRGV2)
Table 7-8. FM Amplitude selection
FM1
0
0
1
1
FM0
0
1
0
1
FM Amplitude /
f_VCO Variation
FM off
±1%
±2%
±4%
7.3.2.8 S12XECRG RTI Control Register (RTICTL)
This register selects the timeout period for the Real Time Interrupt.
Module Base + 0x0007
R
W
Reset
7
RTDEC
0
6
RTR6
5
RTR5
4
RTR4
3
RTR3
2
RTR2
0
0
0
0
0
Figure 7-10. S12XECRG RTI Control Register (RTICTL)
Read: Anytime
Write: Anytime
NOTE
A write to this register initializes the RTI counter.
Table 7-9. RTICTL Field Descriptions
1
RTR1
0
0
RTR0
0
Field
7
RTDEC
6–4
RTR[6:4]
3–0
RTR[3:0]
Description
Decimal or Binary Divider Select Bit — RTDEC selects decimal or binary based prescaler values.
0 Binary based divider value. See Table 7-10
1 Decimal based divider value. See Table 7-11
Real Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI. See Table 7-
10 and Table 7-11.
Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to
provide additional granularity.Table 7-10 and Table 7-11 show all possible divide values selectable by the
RTICTL register. The source clock for the RTI is OSCCLK.
RTR[3:0]
0000 (÷1)
Table 7-10. RTI Frequency Divide Rates for RTDEC = 0
RTR[6:4] =
000
(OFF)
OFF⁽¹⁾
001
(2¹⁰)
2¹⁰
010
(2¹¹)
2¹¹
011
(2¹²)
2¹²
100
(2¹³)
2¹³
101
(2¹⁴)
2¹⁴
110
(2¹⁵)
2¹⁵
111
(2¹⁶)
2¹⁶
MC9S12XHY-Family Reference Manual, Rev. 1.01
270
Freescale Semiconductor