S912XHY128F0VLM Datasheet, PDF (746/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Electrical Characteristics
A.6 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for oscillator and
phase-locked loop (PLL).
A.6.1 Startup
Table A-20 summarizes several startup characteristics explained in this section. Detailed description of the
startup behavior can be found in the Clock and Reset Generator (CRG) block description
Table A-20. Startup Characteristics
Conditions are shown in Table A-4unless otherwise noted
Num C
Rating
Symbol
Min
Typ
1 D Reset input pulse width, minimum input time
PW_RSTL
2
—
2 D Startup from reset
n_RST
192
—
3 D Wait recovery startup time
t_WRS
—
—
4 D Fast wakeup from STOP¹
t_fws
—
50
1 ^{Including voltage regulator startup; V}DD ^/VDDF ^{filter capacitors 220 nF, V}DD35 ^{= 5 V, T= 25°C}
Max
—
196
14
100
Unit
t_osc
n_osc
t_cyc
µs
A.6.1.1 POR
The release level V_PORR and the assert level V_PORA are derived from the V_DD supply. They are also valid
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t_CQOUT no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by n_uposc.
A.6.1.2 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when V_DD35 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG flags register has not been set.
A.6.1.3 External Reset
When external reset is asserted for a time greater than PW_RSTL the CRG module generates an internal
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
A.6.1.4 Stop Recovery
Out of stop the controller can be woken up by an external interrupt. A clock quality check as after POR is
performed before releasing the clocks to the system.
If the MCU is woken-up by an interrupt and the fast wake-up feature is enabled (FSTWKP = 1 and
SCME = 1), the system will resume operation in self-clock mode after t_fws.
MC9S12XHY-Family Reference Manual, Rev. 1.01
746
Freescale Semiconductor