S912XHY128F0VLM Datasheet, PDF (158/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Memory Mapping Control (S12XMMCV4)
3.1.1
Terminology
Table 3-1. Acronyms and Abbreviations
Logic level “1”
Logic level “0”
0x
x
Byte
word
local address
global address
Aligned address
Mis-aligned address
Bus Clock
single-chip modes
normal modes
Voltage that corresponds to Boolean true state
Voltage that corresponds to Boolean false state
Represents hexadecimal number
Represents logic level ’don’t care’
8-bit data
16-bit data
based on the 64KB Memory Space (16-bit address)
based on the 8MB Memory Space (23-bit address)
Address on even boundary
Address on odd boundary
System Clock. Refer to CRG Block Guide.
Normal Single-Chip Mode
Special Single-Chip Mode
Normal Single-Chip Mode
special modes
Special Single-Chip Mode
NS
SS
Unimplemented areas
PRR
PRU
MCU
NVM
IFR
Normal Single-Chip Mode
Special Single-Chip Mode
Areas which are accessible by the pages (RPAGE,PPAGE,EPAGE) and not implemented
Port Replacement Registers
Port Replacement Unit located on the emulator side
MicroController Unit
Non-volatile Memory; Flash, Data FLASH or ROM
Information Row sector located on the top of NVM. For Test purposes.
3.1.2 Features
The main features of this block are:
• Paging capability to support a global 8MB memory address space
• Bus arbitration between the masters CPU, BDM
• Simultaneous accesses to different resources¹ (internal, and peripherals) (see Figure 3-1 )
• Resolution of target bus access collision
• MCU operation mode control
• MCU security control
• Separate memory map schemes for each master CPU, BDM
• ROM control bits to enable the on-chip FLASH or ROM selection
• Generation of system reset when CPU accesses an unimplemented address (i.e., an address which
does not belong to any of the on-chip modules) in single-chip modes
1. ^{Resources are also called targets.}
MC9S12XHY-Family Reference Manual, Rev. 1.01
158
Freescale Semiconductor