S912XHY128F0VLM Datasheet, PDF (261/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12XE Clocks and Reset Generator (S12XECRGV2)
S12X_MMC
Voltage
Regulator
Illegal Address Reset
Power on Reset
Low Voltage Reset
RESET
XCLKS
Clock
Monitor
EXTAL
XTAL
Oscillator
ICRG
CM Fail
OSCCLK
Reset
Generator
Clock Quality
Checker
COP
RTI
V_DDPLL
V_SSPLL
PLLCLK
IPLL
Registers
Clock and Reset Control
Figure 7-1. Block diagram of S12XECRG
7.2 Signal Description
This section lists and describes the signals that connect off chip.
System Reset
Bus Clock
Core Clock
Oscillator Clock
LCD Clock
Real Time Interrupt
PLL Lock Interrupt
Self Clock Mode
Interrupt
7.2.1 V_DDPLL, V_SSPLL
These pins provides operating voltage (V_DDPLL) and ground (V_SSPLL) for the IPLL circuitry. This allows
the supply voltage to the IPLL to be independently bypassed. Even if IPLL usage is not required V_DDPLL
and V_SSPLL must be connected to properly.
7.2.2 RESET
RESET is an active low bidirectional reset pin. As an input it initializes the MCU asynchronously to a
known start-up state. As an open-drain output it indicates that an system reset (internal to MCU) has been
triggered.
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
261