S912XHY128F0VLM Datasheet, PDF (399/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

12.3.1.1 IIC Address Register (IBAD)
Inter-Integrated Circuit (IICV3) Block Description
Module Base +0x0000
7
6
5
4
3
2
1
0
R
0
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-3. IIC Bus Address Register (IBAD)
Read and write anytime
This register contains the address the IIC bus will respond to when addressed as a slave; note that it is not
the address sent on the bus during the address transfer.
Table 12-2. IBAD Field Descriptions
Field
Description
7:1
ADR[7:1]
0
Reserved
Slave Address — Bit 1 to bit 7 contain the specific slave address to be used by the IIC bus module.The default
mode of IIC bus is slave mode for an address match on the bus.
Reserved — Bit 0 of the IBAD is reserved for future compatibility. This bit will always read 0.
12.3.1.2 IIC Frequency Divider Register (IBFD)
Module Base + 0x0001
R
W
Reset
7
IBC7
0
6
IBC6
5
IBC5
4
IBC4
3
IBC3
2
IBC2
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-4. IIC Bus Frequency Divider Register (IBFD)
1
IBC1
0
0
IBC0
0
Read and write anytime
Table 12-3. IBFD Field Descriptions
Field
7:0
IBC[7:0]
Description
I Bus Clock Rate 7:0 — This field is used to prescale the clock for bit rate selection. The bit clock generator is
implemented as a prescale divider — IBC7:6, prescaled shift register — IBC5:3 select the prescaler divider and
IBC2-0 select the shift register tap point. The IBC bits are decoded to give the tap and prescale values as shown
in Table 12-4.
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
399