S912XHY128F0VLM Datasheet, PDF (253/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12X Debug (S12XDBGV3) Module
6.4.5.3 Trace Buffer Organization
Referring to Table 6-40. ADRH, ADRM, ADRL denote address high, middle and low byte respectively.
INF bytes contain control information (R/W, S/D etc.). The numerical suffix indicates which tracing step.
The information format for Loop1 Mode and PurePC Mode is the same as that of Normal Mode. Whilst
tracing in Normal or Loop1 modes each array line contains 2 data entries, thus in this case the DBGCNT[0]
is incremented after each separate entry. In Detail mode DBGCNT[0] remains cleared whilst the other
DBGCNT bits are incremented on each trace buffer entry.
When a COF occurs a trace buffer entry is made and the corresponding CDV bit is set.
Single byte data accesses in Detail Mode are always stored to the low byte of the trace buffer (CDATAL )
and the high byte is cleared. When tracing word accesses, the byte at the lower address is always stored to
trace buffer byte3 and the byte at the higher address is stored to byte2
Table 6-40. Trace Buffer Organization
8-Byte Wide Word Buffer
Mode
7
6
5
4
3
2
1
0
S12XCPU
Detail
CXINF1
CXINF2
CADRH1
CADRH2
CADRM1
CADRM2
CADRL1
CADRL2
CDATAH1 CDATAL1
CDATAH2 CDATAL2
CPU12X
Other Modes
CINF1
CINF3
CPCH1
CPCH3
CPCM1
CPCM3
CPCL1
CPCL3
CINF0
CINF2
CPCH0
CPCH2
CPCM0
CPCM2
CPCL0
CPCL2
MC9S12XHY-Family Reference Manual Rev. 1.01
Freescale Semiconductor
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