S912XHY128F0VLM Datasheet, PDF (52/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Device Overview MC9S12XHY-Family
• the PLL self clocking
• the oscillator
The clock generated by the PLL or oscillator provides the main system clock frequencies core clock and
bus clock. As shown in Figure 1-5, these system clocks are used throughout the MCU to drive the core,
the memories, and the peripherals.
The program Flash memory is supplied by the bus clock and the oscillator clock. The oscillator clock is
used as a time base to derive the program and erase times for the NVMs.
The CAN modules may be configured to have their clock sources derived either from the bus clock or
directly from the oscillator clock. This allows the user to select its clock based on the required jitter
performance.
In order to ensure the presence of the clock the MCU includes an on-chip clock monitor connected to the
output of the oscillator. The clock monitor can be configured to invoke the PLL self-clocking mode or to
generate a system reset if it is allowed to time out as a result of no oscillator clock being present.
In addition to the clock monitor, the MCU also provides a clock quality checker which performs a more
accurate check of the clock. The clock quality checker counts a predetermined number of clock edges
within a defined time window to insure that the clock is running. The checker can be invoked following
specific events such as on wake-up or clock monitor failure.
1.9 Modes of Operation
The MCU can operate in different modes. These are described in 1.9.1 Chip Configuration Summary.
The MCU can operate in different power modes to facilitate power saving when full system performance
is not required. These are described in 1.10.2 Power Modes Low Power Operation.
Some modules feature a software programmable option to freeze the module status whilst the background
debug module is active to facilitate debugging.
1.9.1 Chip Configuration Summary
The different modes and the security state of the MCU affect the debug features (enabled or disabled). The
operating mode out of reset is determined by the state of the MODC signal during reset (see Table 1-9).
The MODC bit in the MODE register shows the current operating mode and provides limited mode
MC9S12XHY-Family Reference Manual, Rev. 1.01
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Freescale Semiconductor