S912XHY128F0VLM Datasheet, PDF (55/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Device Overview MC9S12XHY-Family
1.9.3 Freeze Mode
The timer module, pulse width modulator, and analog-to-digital converters provide a software
programmable option to freeze the module status when the background debug module is active. This is
useful when debugging application software. For detailed description of the behavior of the ATD, TIM,
PWM when the background debug module is active consult the corresponding section.
1.10 Security
The MCU security mechanism prevents unauthorized access to the Flash memory. Refer to Section 5.4.1
Security and Section 15.5 Security
1.11 Resets and Interrupts
Consult the S12X CPU manual and the S12XINT section for information on exception processing.
NOTE
When referring to the S12XINT section please be aware that the XHY
family neither features an XGATE nor an MPU module.
1.11.1 Resets
Table 1-10. lists all Reset sources and the vector locations. Resets are explained in detail in the
Vector Address
$FFFE
$FFFE
$FFFE
$FFFE
$FFFC
$FFFA
Table 1-10. Reset Sources and Vector Locations
Reset Source
CCR
Mask
Local Enable
Power-On Reset (POR)
Low Voltage Reset (LVR)
External pin RESET
Illegal Address Reset
Clock monitor reset
COP watchdog reset
None
None
None
None
None
None
None
None
None
None
PLLCTL(CME,SCME)
COP rate select
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
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