S912XHY128F0VLM Datasheet, PDF (769/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Detailed Register Address Map
0x0000–0x0009 Port Integration Module (PIM) Map 1 of 4
R
0
0
0
0
0
0
0
0
0x0005 Reserved
W
R
0
0
0
0
0
0
0
0
0x0006 Reserved
W
R
0
0
0
0
0
0
0
0
0x0007 Reserved
W
R
0
0
0
0
0
0
0
0
0x0008 Reserved
W
R
0
0
0
0
0
0
0
0
0x0009 Reserved
W
0x000A–0x000B Module Mapping Control (S12XMMC) Map 1 of 2
Address
0x000A
0x000B
Name
Reserved
MODE
Bit 7
R
0
W
R
MODC
W
Bit 6
0
0
Bit 5
0
0
Bit 4
0
0
Bit 3
0
0
Bit 2
0
0
Bit 1
0
0
Bit 0
0
0
0x000C–0x000D Port Integration Module (PIM) Map 2 of 4
Address Name
Bit 7
R
0
0x000C
PUCR
W
R
0
0x000D Reserved
W
Bit 6
BKPUR
0
Bit 5
0
0
Bit 4
0
0
Bit 3
0
0
Bit 2
0
0
Bit 1
PUPBE
0
Bit 0
PUPAE
0
0x000E–0x000F Reserved Register Space
Address Name
Bit 7
R
0
0x000E Reserved
W
R
0
0x000F Reserved
W
Bit 6
0
0
Bit 5
0
0
Bit 4
0
0
Bit 3
0
0
Bit 2
0
0
Bit 1
0
0
Bit 0
0
0
0x0010–0x0017 Module Mapping Control (S12XMMC) Map 2 of 2
Address
0x0010
0x0011
Name
GPAGE
DIRECT
Bit 7
R
0
W
R
DP15
W
Bit 6
GP6
DP14
Bit 5
GP5
DP13
Bit 4
GP4
DP12
Bit 3
GP3
DP11
Bit 2
GP2
DP10
Bit 1
GP1
DP9
Bit 0
GP0
DP8
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
769