S912XHY128F0VLM Datasheet, PDF (267/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12XE Clocks and Reset Generator (S12XECRGV2)
Read: Anytime
Write: Anytime
Table 7-5. CRGINT Field Descriptions
Field
7
RTIE
4
LOCKIE
1
SCMIE
Description
Real Time Interrupt Enable Bit
0 Interrupt requests from RTI are disabled.
1 Interrupt will be requested whenever RTIF is set.
Lock Interrupt Enable Bit
0 LOCK interrupt requests are disabled.
1 Interrupt will be requested whenever LOCKIF is set.
Self Clock Mode Interrupt Enable Bit
0 SCM interrupt requests are disabled.
1 Interrupt will be requested whenever SCMIF is set.
7.3.2.6 S12XECRG Clock Select Register (CLKSEL)
This register controls S12XECRG clock selection. Refer toFigure 7-16 for more details on the effect of
each bit.
Module Base + 0x0005
R
W
Reset
7
PLLSEL
0
6
5
4
3
2
XCLKS
0
0
PSTP
PLLWAI
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-8. S12XECRG Clock Select Register (CLKSEL)
Read: Anytime
Write: Refer to each bit for individual write conditions
1
RTIWAI
0
0
COPWAI
0
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
267