S912XHY128F0VLM Datasheet, PDF (74/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12XHYPIMV1)
1 _{Signals in brackets denote alternative module routing pins.}
2 _{Function active when RESET asserted.}
2.3 Memory Map and Register Definition
This section provides a detailed description of all Port Integration Module registers.
2.3.1 Memory Map
Table 2-2 shows the register map of the Port Integration Module.
Table 2-2. Block Memory Map
Port
Offset or
Address
Register
A 0x0000 PORTA—Port A Data Register
B
0x0001 PORTB—Port B Data Register
0x0002 DDRA—Port A Data Direction Register
0x0003 DDRB—Port B Data Direction Register
0x0004
:
:
0x0009
0x000A
:
0x000B
PIM Reserved
Non-PIM address range¹
A 0x000C PUCR—Pull-up Up Control Register
B
0x000D PIM Reserved
0x000E
:
0x001B
Non-PIM address range¹
0x001C ECLKCTL—ECLK Control Register
0x001D PIM Reserved
0x001E IRQCR—IRQ Control Register
0x001F
0x0020
:
0x023F
PIM Reserved
Non-PIM address range¹
Access Reset Value Section/Page
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R
0x00
2.3.3/2-86
2.3.4/2-87
2.3.5/2-87
2.3.6/2-88
2.3.9/2-90
-
-
R/W²
R/W
-
0x43
0x00
-
-
2.3.8/2-89
2.3.9/2-90
-
R/W
R
R/W²
R
-
0x80
0x00
0x00
0x00
-
2.3.10/2-91
2.3.11/2-91
2.3.12/2-92
2.3.13/2-92
-
MC9S12XHY-Family Reference Manual, Rev. 1.01
74
Freescale Semiconductor