S912XHY128F0VLM Datasheet, PDF (706/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Stepper Stall Detector (SSDV1) Block Description
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Table 21-7. MDCCTL Field Descriptions
Field
7
MCZIE
6
MODMC
5
RDMCL
4
PRE
3
FLMC
2
MCEN
0
AOVIE
Description
Modulus Counter Underflow Interrupt Enable
0 Interrupt disabled.
1 Interrupt enabled. An interrupt will be generated when the modulus counter underflow interrupt flag (MCZIF)
is set.
Modulus Mode Enable
0 The modulus counter counts down from the value in the counter register and will stop at 0x0000.
1 Modulus mode is enabled. When the counter reaches 0x0000, the counter is loaded with the latest value
written to the modulus counter register.
Note: For proper operation, the MCEN bit should be cleared before modifying the MODMC bit in order to reset
the modulus counter to 0xFFFF.
Read Modulus Down-Counter Load
0 Reads of the modulus count register (MDCCNT) will return the present value of the count register.
1 Reads of the modulus count register (MDCCNT) will return the contents of the load register.
Prescaler
0 The modulus down counter clock frequency is the bus frequency divided by 64.
1 The modulus down counter clock frequency is the bus frequency divided by 512.
Note: A change in the prescaler division rate will not be effective until a load of the load register into the modulus
counter count register occurs.
Force Load Register into the Modulus Counter Count Register — This bit always reads zero.
0 Write zero to this bit has no effect.
1 Write one into this bit loads the load register into the modulus counter count register.
Modulus Down-Counter Enable
0 Modulus down-counter is disabled. The modulus counter (MDCCNT) is preset to 0xFFFF. This will prevent an
early interrupt flag when the modulus down-counter is enabled.
1 Modulus down-counter is enabled.
Accumulator Overflow Interrupt Enable
0 Interrupt disabled.
1 Interrupt enabled. An interrupt will be generated when the accumulator overflow interrupt flag (AOVIF) is set.
21.3.2.3 Stepper Stall Detector Control Register (SSDCTL)
Module Base + 0x0002
R
W
Reset
7
RTZE
0
Read: anytime
Write: anytime
6
5
4
3
2
1
0
0
0
SDCPU
SSDWAI
FTST
ACLKS
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 21-4. Stepper Stall Detector Control Register (SSDCTL)
MC9S12XHY-Family Reference Manual, Rev. 1.01
706
Freescale Semiconductor