S912XHY128F0VLM Datasheet, PDF (277/802 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12XE Clocks and Reset Generator (S12XECRGV2)
Table 7-14. Examples of IPLL Divider Settings
f_OSC REFDIV[5:0] f_REF REFFRQ[1:0] SYNDIV[5:0] f_VCO VCOFRQ[1:0] POSTDIV[4:0] f_PLL
f_BUS
4MHz
$01
2MHz
01
$18
100MHz
11
$00
100MHz 50 MHz
8MHz
$03
2MHz
01
$18
100MHz
11
$00
100MHz 50 MHz
4MHz
$00
4MHz
01
$09
80MHz
01
$00
80MHz 40MHz
8MHz
$00
8MHz
10
$04
80MHz
01
$00
80MHz 40MHz
4MHz
$00
4MHz
01
$03
32MHz
00
$01
16MHz 8MHz
4MHz
$01
2MHz
01
$18
100MHz
11
$01
50MHz 25MHz
4MHz
$03
1MHz
00
$18
50MHz
01
$00
50MHz 25MHz
4MHz
$03
1MHz
00
$31
100MHz
11
$01
50MHz 25MHz
7.4.1.1.1 IPLL Operation
The oscillator output clock signal (OSCCLK) is fed through the reference programmable divider and is
divided in a range of 1 to 64 (REFDIV+1) to output the REFCLK. The VCO output clock, (VCOCLK) is
fed back through the programmable loop divider and is divided in a range of 2 to 128 in increments of [2
x (SYNDIV +1)] to output the FBCLK. The VCOCLK is fed to the final programmable divider and is
divided in a range of 1,2,4,6,8,... to 62 (2*POSTDIV) to output the PLLCLK. See Figure 7-15.
The phase detector then compares the FBCLK, with the REFCLK. Correction pulses are generated based
on the phase difference between the two signals. The loop filter then slightly alters the DC voltage on the
internal filter capacitor, based on the width and direction of the correction pulse.
The user must select the range of the REFCLK frequency and the range of the VCOCLK frequency to
ensure that the correct IPLL loop bandwidth is set.
The lock detector compares the frequencies of the FBCLK, and the REFCLK. Therefore, the speed of the
lock detector is directly proportional to the reference clock frequency. The circuit determines the lock
condition based on this comparison.
If IPLL LOCK interrupt requests are enabled, the software can wait for an interrupt request and then check
the LOCK bit. If interrupt requests are disabled, software can poll the LOCK bit continuously (during
IPLL start-up, usually) or at periodic intervals. In either case, only when the LOCK bit is set, the PLLCLK
can be selected as the source for the system and core clocks. If the IPLL is selected as the source for the
system and core clocks and the LOCK bit is clear, the IPLL has suffered a severe noise hit and the software
must take appropriate action, depending on the application.
• The LOCK bit is a read-only indicator of the locked state of the IPLL.
• The LOCK bit is set when the VCO frequency is within a certain tolerance, ∆_Lock, and is cleared
when the VCO frequency is out of a certain tolerance, ∆_unl.
• Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling
the LOCK bit.
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
277