TCI6630K2L Datasheet, PDF (87/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
Table 7-22. System Event Mapping — C66x CorePac Primary Interrupts (continued)
EVENT NO.
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
EVENT NAME
GPIO_INTN
CIC_OUT12_PLUS_16_MUL_N
CIC_OUT34
CIC_2_OUT13
MDMAERREVT
Reserved
EDMACC_0_TC_AET_INT
PMC_ED
EDMACC_1_TC_AET_INT
EDMACC_2_TC_AET_INT
UMC_ED1
UMC_ED2
PDC_INT
SYS_CMPA
PMC_CMPA
PMC_DMPA
DMC_CMPA
DMC_DMPA
UMC_CMPA
UMC_DMPA
EMC_CMPA
EMC_BUSERR
DESCRIPTION
GPIO interrupt
CIC Interrupt Controller output⁽¹⁾
CIC Interrupt Controller output⁽¹⁾
CIC Interrupt Controller output⁽¹⁾
DMA internal bus error event
EDMA3CC0 AET event
Single bit error detected during DMA read
EDMA3CC1 AET event
EDMA3CC2 AET event
Corrected bit error detected
Uncorrected bit error detected
Power down sleep interrupt
SYS CPU MP fault event
CPU memory protection fault
DMA memory protection fault
CPU memory protection fault
DMA memory protection fault
CPU memory protection fault
DMA memory protection fault
CPU memory protection fault
Bus error interrupt
NOTE
Event No. 0 is identical to ARM GIC interrupt ID 0.
Table 7-23 lists the ARM CorePac event inputs
EVENT NO.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Table 7-23. System Event Mapping — ARM CorePac Interrupts
EVENT NAME
RSTMUX_INT8
RSTMUX_INT9
Reserved
Reserved
IPC_GR8
IPC_GR9
Reserved
Reserved
SEM_INT8
SEM_INT9
Reserved
Reserved
SEM_ERR8
SEM_ERR9
Reserved
DESCRIPTION
Boot config watchdog timer expiration (timer 16) event for ARM Core 0
Boot config watchdog timer expiration (timer 17) event for ARM Core 1
Boot config IPCG
Boot config IPCG
Semaphore interrupt
Semaphore interrupt
Semaphore error interrupt
Semaphore error interrupt
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Memory, Interrupts, and EDMA for TCI6630K2L
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