TCI6630K2L Datasheet, PDF (83/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

www.ti.com
TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
Table 7-21. MPU12-MPU15 Programmable Range n Memory Protection Page Attribute Register
(PROGn_MPPAR) Reset Values (continued)
REGISTER
PROG15_MPPAR
MPU12
N/A
MPU13
N/A
MPU14
N/A
MPU15
0x03FF_FCB6
7.3 Interrupts for TCI6630K2L
This section discusses the interrupt sources, controller, and topology. Also provided are tables describing
the interrupt events.
7.3.1 Interrupt Sources and Interrupt Controller
The CPU interrupts on the TCI6630K2L device are configured through the C66x CorePac Interrupt
Controller. The Interrupt Controller allows for up to 128 system events to be programmed to any of the 12
CPU interrupt inputs (CPUINT4 - CPUINT15), the CPU exception input (EXCEP), or the advanced
emulation logic. The 128 system events consist of both internally-generated events (within the CorePac)
and chip-level events.
Additional system events are routed to each of the C66x CorePacs to provide chip-level events that are
not required as CPU interrupts/exceptions to be routed to the Interrupt Controller as emulation events. In
addition, error-class events or infrequently used events are also routed through the system event router to
offload the C66x CorePac interrupt selector. This is accomplished through the two CorePac Interrupt
Controller blocks, CIC0 and CIC2. These CIC are clocked using CPU/6.
The event controllers consist of simple combination logic to provide additional events to each C66x
CorePac, ARM GIC (ARM Generic Interrupt Controller) plus the EDMA3CC. CIC0 has 104 event outputs
which provides 20 broadcast events and 18 additional events to each of the C66x CorePacs, 0 through 3.
CIC1 is reserved. CIC2 has 103 event outputs which provides 8, 20, and 8 events to EDMA3CC0,
EDMA3CC1, and EDMA3C2 respectively.
The events that are routed to the C66x CorePacs for Advanced Event Triggering (AET) purposes, from
those EDMA3CC and FSYNC events that are not otherwise provided to each C66x CorePac.
Modules such as FFTC, TCP3d, TAC, CP_MPU (Coprocessor Memory Protection Unit), BOOT_CFG, and
CP_Tracer have level interrupts and EOI handshaking interface. The EOI value is 0 for TCP3d_x, TAC,
CP_MPU, BOOT_CFG, and CP_Tracer.
For FFTC:
• the EOI value is 0 for FFTC_x_INTD_INTR0,
• the EOI value is 1 for FFTC_x_INTD_INTR1,
• the EOI value is 2 for FFTC_x_INTD_INTR2
• the EOI value is 3 for FFTC_x_INTD_INTR3 (where FFTC_x can be FFTC_0 or FFTC_1)
Figure 7-5 shows the TCI6630K2L interrupt topology.
Copyright © 2013–2015, Texas Instruments Incorporated
Memory, Interrupts, and EDMA for TCI6630K2L
83
Submit Documentation Feedback
Product Folder Links: TCI6630K2L