TCI6630K2L Datasheet, PDF (241/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
Figure 11-10. PLL Controller Divider Register (PLLDIVn)
31
16
15
14
Reserved
Dn⁽¹⁾ EN
R-0
R/W-1
Legend: R/W = Read/Write; R = Read only; -n = value after reset
(1) D3EN for PLLDIV3; D4EN for PLLDIV4
(2) n=02h for PLLDIV3; n=03h for PLLDIV4
Reserved
R-0
8
7
0
RATIO
R/W-n ⁽²⁾
Bit
31-16
15
Field
Reserved
DnEN
14-8
7-0
Reserved
RATIO
Table 11-17. PLL Controller Divider Register Field Descriptions
Description
Reserved
Divider Dn enable bit (See footnote of Figure 11-10)
• 0 = Divider n is disabled
• 1 = No clock output. Divider n is enabled.
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Divider ratio bits (See footnote of Figure 11-10)
• 0h = ÷1. Divide frequency by 1
• 1h = ÷2. Divide frequency by 2
• 2h = ÷3. Divide frequency by 3
• 3h = ÷4. Divide frequency by 4
• 4h - 4Fh = ÷5 to ÷80. Divide frequency range: divide frequency by 5 to divide frequency by 80.
11.5.3.3 PLL Controller Clock Align Control Register (ALNCTL)
The PLL Controller Clock Align Control Register (ALNCTL) is shown in Figure 11-11 and described in
Table 11-18.
Figure 11-11. PLL Controller Clock Align Control Register (ALNCTL)
31
5
4
32
0
Reserved
ALN4 ALN3
Reserved
R-0
R/W-1 R/W-1
R-0
Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value
Table 11-18. PLL Controller Clock Align Control Register Field Descriptions
Bit
31-5
2-0
4
3
Field
Reserved
ALN4
ALN3
Description
Reserved. This location is always read as 0. A value written to this field has no effect.
SYSCLK n alignment. Do not change the default values of these fields.
• 0 = Do not align SYSCLK n to other SYSCLKs during GO operation. If SYS n in DCHANGE is set, SYSCLK n
switches to the new ratio immediately after the GOSET bit in PLLCMD is set.
• 1 = Align SYSCLK n to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set and SYS
n in DCHANGE is 1. The SYSCLK n rate is set to the ratio programmed in the RATIO bit in PLLDIV n.
11.5.3.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
Whenever a different ratio is written to the PLLDIV n registers, the PLL CTL flags the change in the
DCHANGE Status Register. During the GO operation, the PLL controller changes only the divide ratio of
the SYSCLKs with the bit set in DCHANGE. Note that the ALNCTL Register determines if that clock also
needs to be aligned to other clocks. The PLLDIV Divider Ratio Change Status Register is shown in
Figure 11-12 and described in Table 11-19.
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TCI6630K2L Peripheral Information and Electrical Specifications 241
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