TCI6630K2L Datasheet, PDF (269/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

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TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
Table 11-53. UART Switching Characteristics
(see Figure 11-51 and Figure 11-52)
NO.
PARAMETER
MIN
MAX
1
tw(TXSTART)
Transmit Timing
Pulse width, transmit start bit
U ⁽¹⁾- 2
U+2
2
tw(TXH)
Pulse width, transmit data/parity bit high
U-2
U+2
2
tw(TXL)
Pulse width, transmit data/parity bit low
U-2
U+2
3
tw(TXSTOP1)
Pulse width, transmit stop bit 1
U-2
U+2
3
tw(TXSTOP15)
Pulse width, transmit stop bit 1.5
1.5 * (U - 2) 1.5 * ('U + 2)
3
tw(TXSTOP2)
Pulse width, transmit stop bit 2
2 * (U - 2) 2 * ('U + 2)
7
td(RX-RTSH)
Autoflow Timing Requirements
Delay time, STOP bit received to RTS deasserted
P ⁽²⁾
5P
(1) U = UART baud time = 1/programmed baud rate
(2) P = 1/(SYSCLK1/6)
UNIT
ns
ns
ns
ns
ns
ns
ns
1
2
2
3
TXD
Stop/Idle
Start
Bit 0
Bit 1
Bit N-1 Bit N
Parity
Stop
Idle
Start
Figure 11-51. UART Transmit Timing Waveform
7
RXD
Bit N-1 Bit N
Stop
Start
CTS
Figure 11-52. UART RTS (Request-to-Send Output) – Autoflow Timing Waveform
11.15 PCIe Peripheral
The two-lane PCI express (PCIe) module on TCI6630K2L provides an interface between the device and
other PCIe-compliant devices. The PCIe module provides low pin-count, high-reliability, and high-speed
data transfer at rates up to 5.0 Gbps per lane on the serial links. For more information, see the KeyStone
Architecture Peripheral Component Interconnect Express (PCIe) User's Guide (SPRUGS6).
11.16 Packet Accelerator
The Packet Accelerator (PA) provides L2 to L4 classification functionalities and supports classification for
Ethernet, VLAN, MPLS over Ethernet, IPv4/6, GRE over IP, and other session identification over IP such
as TCP and UDP ports. It maintains 8k multiple-in, multiple-out hardware queues and also provides
checksum capability as well as some QoS capabilities. The PA enables a single IP address to be used for
a multicore device and can process up to 1.5 Mpps. The Packet Accelerator is coupled with the Network
Coprocessor. For more information, see the KeyStone II Architecture Packet Accelerator 2 (PA2) for K2E
and K2L Devices User's Guide (SPRUHZ2).
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TCI6630K2L Peripheral Information and Electrical Specifications 269
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