TCI6630K2L Datasheet, PDF (194/298 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip

TCI6630K2L
SPRS893E – MAY 2013 – REVISED JANUARY 2015
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9.2.3.17 IPC Generation Host (IPCGRH) Register
The IPCGRH register facilitates interrupts to external hosts. Operation and use of the IPCGRH register is
the same as for other IPCGR registers. The interrupt output pulse created by the IPCGRH register
appears on device pin HOUT.
The host interrupt output pulse is stretched so that it is asserted for four bootcfg clock cycles (SYSCLK1/6)
followed by a deassertion of four bootcfg clock cycles. Generating the pulse results in a pulse-blocking
window that is eight SYSCLK1/6-cycles long. Back-to-back writes to the IPCRGH register with the IPCG
bit (bit 0) set, generates only one pulse if the back-to-back writes to IPCGRH are less than the eight
SYSCLK1/6 cycle window — the pulse blocking window. To generate back-to-back pulses, the back-to-
back writes to the IPCGRH register must be written after the eight SYSCLK1/6 cycle pulse-blocking
window has elapsed. The IPC Generation Host Register is shown in Figure 9-29 and described in Table 9-
45.
Figure 9-29. IPC Generation Registers (IPCGRH)
31
SRCS27 - SRCS0
RW +0 (per bit field)
Legend: R = Read only; RW = Read/Write; -n = value after reset
4
3
0
Reserved
R-0000
Bit
31-4
Field
SRCSx
3-1 Reserved
0
IPCG
Table 9-45. IPC Generation Registers Field Descriptions
Description
Reads return current value of internal register bit.
Writes:
• 0 = No effect
• 1 = Sets both SRCSx and the corresponding SRCCx.
Reserved
Reads return 0.
Writes:
• 0 = No effect
• 1 = Creates an interrupt pulse on device pin (host interrupt/event output in HOUT pin)
9.2.3.18 IPC Acknowledgment Host (IPCARH) Register
The IPCARH register facilitates external host interrupts. Operation and use of the IPCARH register is the
same as for other IPCAR registers. The IPC Acknowledgment Host Register is shown in Figure 9-30 and
described in Table 9-46.
Figure 9-30. Acknowledgment Register (IPCARH)
31
SRCC27 - SRCC0
RW +0 (per bit field)
Legend: R = Read only; RW = Read/Write; -n = value after reset
4
3
0
Reserved
R-0000
Bit
31-4
Field
SRCCx
3-0 Reserved
Table 9-46. IPC Acknowledgment Register Field Descriptions
Description
Reads the return current value of the internal register bit.
Writes:
• 0 = No effect
• 1 = Clears both SRCCx and the corresponding SRCSx
Reserved
194 Device Boot and Configuration
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